1. Field of the Invention
The present invention relates to a semiconductor circuit device and a method of using the same. More specifically, the present invention relates to a synchronous semiconductor memory device operating in synchronization with an external clock signal.
2. Description of the Background Art
A synchronous dynamic random access memory (hereinafter referred to as an "SDRAM") is one example of semiconductor circuit devices operating in synchronization with an external clock signal. A conventional SDRAM is provided with a CMOS type output buffer circuit as shown in FIG. 11.
Referring to FIG. 11, the output buffer circuit includes a P channel MOS transistor 1 and an N channel MOS transistor 2. P channel MOS transistor 1 is connected between an external power supply node 3 receiving an external power supply voltage EVCC and an output node 4 and has its gate connected to an input node 5. N channel MOS transistor 2 is connected between a ground node 6 receiving a ground voltage GND and output node 4 and has its gate connected to input node 5.
When an L (logic low) level output signal VOUT which was read out of a memory cell array is received at input node 5, P channel MOS transistor 1 and N channel MOS transistor 2 are turned on and off, respectively, and thus an H (logic high) level data signal DQn is output from output node 4.
On the other hand, when H level output signal VOUT is input to input node 5, P channel MOS transistor 1 and N channel MOS transistor 2 are turned off and on, respectively, and thus L level data signal DQn is output from output node 4.
Since an SDRAM is usually employed as a memory device for a computer system, external clock signals having various frequencies are input to the SDRAM according to the operating frequency of a CPU (Central Processing Unit). Therefore, the sizes of transistors 1 and 2 are usually so designed that the output buffer circuit can supply sufficient current when an external clock signal having a maximum frequency is input.
However, when the frequency of the external clock signal is low, the current supplying capability of the output buffer circuit becomes too high. Therefore, a ringing phenomenon has been caused before data signal DQn converges at the H or L level.
Although Japanese Patent Laying-Open No. 2-92019 discloses the technique of setting a mode register in accordance with the load of external circuitry connected to a terminal for outputting a data signal and changing the drivability of an output buffer circuit in accordance with the set mode register, the problem above cannot be solved since what is set in the mode register is a signal which corresponds to the "load" of the external circuitry.